The present invention relates to a compound semiconductor device and a method of making the compound semiconductor device.
Semiconductor devices include diodes having two electrodes and transistors having three or more electrodes. Prior to description of the invention, a method of making a field-effect transistor (FET) in the prior art is described with reference to FIG. 6A to FIG. 6F. This method is disclosed in the Technical paper of the institute of Electronics and Communication Engineers of Japan, ED 85-101, Nov. 22, 1985, pages 1 to 6. The method is for forming a GaAs FET and is called the through-implantation method. FIG. 6A to FIG. 6F are sectional diagrams at various process steps of the through-implantation method.
First, ions are selectively injected into a semi-insulating GaAs substrate 10 to form an n-type layer 12 (FIG. 6A). Then, an SiO.sub.2 film 14 is formed to a suitable thickness by a CVD method over an area where a gate electrode will be formed (FIG. 6B). Then, optical lithography is used to form an n.sup.+ -type layer 16 (FIG. 6C). That is, a resist layer is first formed, and a resist pattern 18 having an opening over an area including the SiO.sub.2 film 14 and its surrounding region is formed, and Si is heavily ion-implanted using the resist pattern 18 and the SiO.sub.2 film 14 as a mask, to form the n.sup.+ -type layer 16. The SiO.sub.2 layer 14 acts as a partial mask: some Si ions pass through the n.sup.+ -type layer 14 and a shallow n.sup.+ -type layer 16b is formed under the SiO.sub.2 layer 14. A deep n.sup.+ -type layer 16a is formed in the region surrounding the SiO.sub.2 layer 14. The layer 16 is the aggregate of the layers 16a and 16b.
The SiO.sub.2 layer 14 and the resist pattern 18 are then removed, and the substrate is annealed, and source and drain electrodes 20 and 22 are formed (FIG. 6D). A resist is formed over the n.sup.+ -type layer 16, and a resist pattern 26 is formed by optical lithography. The resist pattern 26 has an opening 24 over the area where the gate electrode will be formed. Isotropic, wet etching is then performed using the resist pattern 26 as a mask to recess-etch the n.sup.+ -type layer 16b and the n-type layer 12 to form a structure having a recess 28 (FIG. 6E). A gate metal is vapor-deposited in the vertical direction, using the resist pattern 26 as a mask, to form a gate electrode 30. The resist pattern 26 is thereafter removed to form an FET structure (FIG. 6F). FIG. 7 shows, in an enlarged scale, the gate electrode and its surrounding structure.
In the example described above, the isotropic etching is employed in a method of making GaAs FET in which ion implantation is also used. The process employing the isotropic etching can be used in a method of making an n.sup.+ /n (such as n.sup.+ /n GaAs, n.sup.+ /n InP or n.sup.+ /n Ge) MES FET where an epitaxial method is also used, and a method of making a n.sup.+ GaAs/n AlGaAs HEMT (high electron mobility transistor) and the like.
In the process of forming the gate electrode 30, the resist pattern 26 is used as a mask during the isotropic etching to form the recess 28 reaching the n-type layer 12, and gate metal is vapor-deposited vertically, so that the gate electrode will be symmetrical.
As will be seen from FIG. 7, the distance .beta. between the lower edge of the gate electrode 30 where it is in contact with the n-type layer 12 and the boundary between the n-type layer 12 and the n.sup.+ -type layer 16b, along the bottom surface 28a and the inclined side surface 28b of the recess 28 is long, so that the source resistance of the FET is high. The mutual conductance is therefore low, degrading the FET characteristics.
Moreover, if the adhesion of the resist pattern 26 to the substrate 10 is not adequate the n.sup.+ -type layer 16b and the n-type layer 12 under the resist pattern 26 is side-etched, and the above-mentioned distance is increased. The side-etching may extend up to the area .alpha. where the source electrode 20 is provided.
Furthermore, where the carrier concentration in the layers 16b and 12 is changed due to heat treatment after the ion-implantation, the amount of the recess-etching varies, and the above-mentioned distance .beta. is changed. As a result, the reproducibility of the source resistance is low.